This is the transcript of a talk I gave in Siena on 26 June 2015, for the annual meeting of the Italian association of scholars and researchers in Electronics (“Gruppo Italiano Elettronica”).
Semiconductor electronics was shaped in a form very close to the present one between the 30s and the 60s, as a distinct discipline with respect to solid-state physics and vacuum-tube electronics. During those developments it became clear that some electrical engineers had to be trained as scientists, and the first PhD program for engineers was started at MIT in 1952 after the initiative of Gordon Brown, then Head of the Department of Electrical Engineering.
Already in 1932, in a paper on Zeitschift fur Physik on the theory of metal-semiconductor diodes, we see a illustration of the principle of operation using the now common band-edge profiles.
And this is a photo of Shockley from 1950, where we can clearly see the band-edge profiles of a bipolar junction transistor. This graphic way of describing the operation of semiconductor devices became common in the 30s. Basically, if you take a modern textbook or some modern papers, you find a very similar way of describing transistor operation.
Why semiconductor electronics has be so successful for such a long time? Let’s look at what happened. Bardeen, Brattain and Shockley invented the first transistor in 1948. They actually were trying to obtain a field-effect transistor, but it worked out differently, and they obtained the point-contact transistors.
The first transistor made of germanium one, then silicon became the material of choice, right after the invention of the integrated circuit by Kilby and Noyce. Silicon oxide was a very good dielectric and could be grown on silicon.
The integrated circuit allow the industry to double every 1–2 years the number of transistors on a single chip. And it is still working now, at a few billion transistors per chip. This exponential behaviour came to be known as Moore’s law, after a prediction that Gordon Moore made in 1965, with only few data points, exactly 50 years ago.
Actually, after moving from Bipolar devices to NMOS and to CMOS, the track to scaling was well defined. I do not want to discard the huge investment in technology that was required, but from the device point of view, little changed in terms of materials and geometries except for scaling.
But in the 80s already someone started to see that scaling was becoming harder, and that therefore some intrinsic limitations were present. Some alternatives were proposed: one very interesting at the time was the so-called bandgap engineering, which was proposed among others by Federico Capasso, then at Bell Labs. The core of the proposal was to exploit the newly available growth techniques to fabricated heterostructures and superlattices in order to adjust the bandstructures to optimize existing devices or create new device concepts.Actually it did not go this way and it never made into the mainstream in this form. The semiconductor industry found new ways to proceed with the scaling down, leaving the device structure unaltered.
But then, something happened 12 years ago. Scaling continued, but strong innovations had to be introduced in terms of materials and structure.
First, in 2003, strained silicon. We stretch the silicon crystal to modify the bandstructure, to adjust the energy of conduction band minima and valence band maxima, and to modify the effective mass, in order to boost mobility. Tensile strain is needed for PMOS, compressive strain for NMOS. You can see, this is essentially a type of bandstructure engineering, which actually became mainstream, in a way different from what initially proposed.
Then in 2007, High-K metal gate process, another type of bandgap engineering. A gate stack with insulator with high dielectric constant and smaller gap, that would allow to use a thicker layer to suppress gate leakage current while maintaining good electrostatic control on the channel.
Finally, in 2011, the trigate process, i.e. no more planar transistors but a three dimensional device, to improve the electrostatic control of the channel.
In the end we really do not recognize a transistor anymore. What’s this?
You see, the image of a 22 nm transistor is closer to a molar than to a 130 nm transistor. It is definitely not your dad’s transistor.
What should we expect now?
Simply, more of the same:
- more innovation in materials, for example III-V semiconductors, Germanium, or other 2D materials for the transistor channel
- more innovation in structures, for example the use of 3D structures, which is now a reality in non-volatile memories.
- more physical mechanisms, adding to transport and electrostatics also mechanics, microfluidics, optics, magnetics, piezo, thermoelectrics. For example microelectromechanical systems are already a 12 B$ global business.
Now it should be clear what is The New Semiconductor Electronics.
We had a semiconductor electronics with few materials, mainly the silicon-silicon oxide system, planar devices, and only electronics on a silicon chip.
The New Semiconductor Electronics uses a wealth of materials, geometries, and much more physical mechanisms on a silicon platform
Of course it is a huge intellectual adventure, because we need to change skin a bit, and to learn lots of new things.
Are we ready for this?
I don’t know. In the 60s, when Semiconductor Electronics was established as a distinct discipline, the Semiconductor Electronics Education Committee was established to prepare a set of six paperback textbooks to teach the subject in an adequate way.
I am trying to buy all those books from abebooks. If you read them you would notice that they are very similar to the books we use today, 50 years later.
We need some effort in renewing academic education and research in the field of semiconductor electronics.
Things have not only become more complicate in the new semiconductor electronics. Indeed, other things are simpler at the nanoscale!
For example, in traditional semiconductor electronics we look at bipolar junction transistors and at field-emission transistors as different devices, the former dominated by diffusion currents, and the second by drift currents.
However, for small channel length, if we look at the band edge profiles of the two devices, as shown in the figure below, we clearly see that they are identical, and that both devices are described by the same physical mechanism: thermionic emission over a tunable barrier.
As far as noise is concerned, we learn from traditional device electronics book that shot noise describes the current noise in a bipolar transistor, and that “corrected” thermal noise describes current noise in a field-effect transistor. However, it is well known that as channel length is decreases the latter correction becomes larger and larger, in order to enable the model to reproduce reality.
The fact is that in nanoscale FETs the operating mechanism is similar as that of a bipolar transistor, and therefore “suppressed” shot noise is the proper noise mechanism also describing an FET. The “suppression” is due to the proximity of the gate contact.
This concept has been clearly expressed more than 10 years ago, and finally in recent years it has been demonstrated in experiments on 10-nm long FETs.
As a third example, let me show this figure from Willy Sansen’s keynote at ISSCC in 2015. For analog circuit design in aggressively scaled down CMOS processes, below 20 nm: subthreshold operation provides the best figures of merit in terms of performance at power parity (the corresponding figure of merit is the cutoff frequency times the transconductance divided by the bias current).
This is very interesting, because in traditional undergraduate education the subthreshold operation of field-effect transistor is often not considered. In sub threshold operation, currents depend exponentially on bias voltages, as in bipolar transistors.
I would like now to give some examples of how we address the themes of the new semiconductor electronincs.
In the last decade, two dimensional materials have attracted incredible interest for applications in electronics. It all started when the electrical properties of graphene where discovered and characterized in 2004 in Manchester. Graphene is just one-atom thick, therefore is an ideal two-dimensional material, and can have a very high mobility at room temperature, close to 10,000 cm2/Vs when deposited on a substrate. However, it also have a zero energy gap, which represents a severe obstacle to its use in electronics.
After graphene, other two-dimensional materials have received enormous attention: among them boron nitride, the family of transition metal dichalcogenides, bismuth selenide and bismuth telluride, and others.
They are also very thin, generally have a medium-to-low mobility and have an energy gap from 0.1 eV to 5 eV, with the usual tradeoff between mobility and energy gap.
If we look at performance figures, such as the delay time and the dynamic power indicator, they are in the optimistic case in line with the evolution of the International Tecnology Roadmap for Semiconductor, since device modeling on defect less device structures predict comparable performance to the expectations at the end of roadmap horizon (2016).
In 2012, a “Materials on demand” Paradigm has been proposed, i.e., the possibility of obtaining 3D materials with taylored properties by stacking several layers of 2D materials coupled by Var der Waals forces.
You can probably recognize the similarity with the paradigm of “Bandgap Engineering” of the 80s that I have shown before. Of course, things are not identical: in the 80s they were considering III-V heterostructures, consisting of layers with a thickness of few nanometers, almost lattice-matched; in this case we are dealing with single atom layers, often with completely different lattice, and we are playing with a larger number of atomic species. Of course, history does not exactly repeat itself, but it rhymes?—?as Mark Twain famously said.
Let me say how we address these problems. Our specialty is the early assessment of device potential via modelling. In order to do that, we use our in house simulation tool, Nanotcad Vides, that now has 15 years of development. It started with a European project that I coordinated in the 5th Framework Programme from 2000 to 2003, and now has atomistic simulation capabilities of 3D devices coupling transport and electrostatics. Now the lead developer is my colleague Gianluca Fiori, we have made freely available the source code and full documentation, to let everybody use it. As of today, a few groups are using this code, also independently of us. We maintain a known list of publications using the code.
With the code we can compute transport properties of silicon and carbon based devices, using non-equilibrium Green’s functions with a tight-binding Hamiltonian, or an effective mass approach. To put it simply, we build the device or key building blocks atom by atom, and then simulate the operation of a complete device.
Our approach is to use our modeling tools, other tools, and analytical modeling to evaluate the feasibility and the possible performance of a device structure (assuming that fabrication problems will be solved). Here a mix of physicist and engineer attitude is really important. We look at new effects for opportunities, we are optimistic but skeptic, and we benchmark with existing technology and its foreseeable evolution, as for example predicted by the International Technology Roadmap for Semiconductors.
Essentially, we use a “Via Negativa” approach: we try to rapidly filter out device structures and operating principle that are not promising, and save the very few promising ones for further investigation.
Via negativa: “This won’t work. This neither. Try instead this.”
In the modern scientific PR-conscious world where hype is the norm, saying that some things do not work is not the easy way to become popular.
I need to add few more words on our methodology. We need to consider many different materials, and of some of them we have very limited information. In addition, the materials properties are affected by the by the peculiar heterostructure we choose. We then need a way to compute material properties and to use those results in the device simulations.
This requires a specific multiscale simulation procedure because ab initio quantum chemisty tools (DFT) for the calculation of material properties are very demanding from the computational point of view.
For this reason, we have recently defined this multiscale methodology according to which we use an open source DFT tool (e.g., Quantum Espresso) to make ab initio calculations, in order to compute materials properties. Once we have a good single particle Hamiltonian, we derive a TB Hamiltonian, using Wannier90 to project the Hamiltonian on a basis of localized Wannier functions. Finally, we can perform NEGF calculations with our in-house code.
In the rest of this talk, I just want to use my time to show you a device that after our via negativa test is still promising for application, to come close to an end in a positive note.
The lateral heterostructure field-effect transistor is a transistor structure we proposed in 2011. The channel consists of a lateral heterostructure, where we have on the same single sheet regions of graphene and regions of another 2D material with comparable lattice. In our case, the part of the channel under the gate is made of a large gap material, such as boron nitride, because it has to stop the current in the off state, and outer regions of source and drain are made with graphene.
In 2012 a paper from Cornell demonstrated in experiments the possibility to pattern lateral graphene-boron nitride heterostructures, with graphene patterning and successive CVD regrowth of boron nitride. There were only limited electrical measurement in the original paper.
However, in 2013 this concept was demonstrated by this paper from HRL Laboratories where they used as a central region fluorinated graphene. The device works with very good Ion/Ioff ratio.
We used density-functional theory to obtain the band structure for different types of central region, and in the end we chose BC2N, which is lattice matched to graphene, and provides a valence band offsed with respect to graphene Dirac point of 0.64 eV.
If we want to compare the potential of these devices with CMOS, we need to look at the expectations of the ITRS, 2012 edition, since it only deals with planar transistors.
Let us consider the table below, showing expectation for high performance CMOS process (HP) and for low power CMOS (LP), from 2014 to 2026.
Gate length is shrinking from 22 to 6 nm, and the supply voltage is going down to half a volt. The ratio of the “on” current (Ion) to “off” current (Ioff) is larger than 10^4.
From the point of view of dynamic performance, we have two figures of merit: the delay time, which is the ratio of the charge variation in the device between the “on” state and the “off” state, to the “on” current. And the power delay product (or dynamic power indicator), which is the product of the supply voltage, Ion and the delay time.
The delay time is a measure of speed, of computational performance. The power-delay product is a measure of energy efficiency.
As you see here CMOS are expected to remain in the fraction of ps for delay time and fraction of femtojoule per micron for the PDP.
Now, we can compare at least LHFET with the ITRS2012. We chose the ITRS version because it focuses on planar transistors. The blue signs are for the high performance process, the red symbols for Low Power. We plot the On current, delay time, and power delay product as a function of the year of introduction. And we also include the BCN LHFETs with green triangles inserting them at the same year of introduction of the CMOS process with the same gate length.
You see, the delay time is better than in the case of HP CMOS, and the power-delay product is better than LP CMOS. Of course we are here considering defectless ballistic devices. But still, it is important, because the transistors based on vertical heterostructure of 2D materials, even in the most optimistic situation, provide for example a delay time that is orders of magnitude higher. More details can be found in a dedicated paper.
I am going to conclude now. The new semiconductor electronics represents a huge intellectual challenge, requiring us to address new materials, new geometries, and new physical mechanisms.
Therefore, we need to build a consistent body of knowledge drawing concepts from engineering, physics, and chemistry, and streamlining the interfaces between such disciplines. We have also to find ways to teach this new body of knowledge.
p.s. I have an intellectual debt to the whitepaper of the Electronics from the Bottom up Initiative by Mark Lundstrom, Supriyo Datta, Ashraf Alam (2007), for laying out the need of a new SEEC effort.